Digitabulum: Flex circuits, and a release choice
2017-01-05 23:46 by Ian
After 1.5 years, the digit design is complete, and is real hardware on my desk. This was easily the hardest (and most expensive) part of the project.
Digitabulum: Digit update
2016-12-14 01:48 by Ian
First articles of the flex parts arrived today. This is a panel as it arrives at the assembly house. This one was shipped to me as a representative sample that I can use for testing some EE parameters.
Securely wiping data with minimal tools
2016-11-21 23:27 by Ian
This was an email I wrote to some coworkers explaining how I securely wipe data. I am reproducing it here.
Digitabulum: Final digit layout
2016-10-19 02:13 by Ian
Fabricator is ready to roll with the flex circuits, after a looooong game of ping-pong and a few re-work cycles. Getting things right in such tight constraints was not a trivial task. And after more than a year of refinement, the digits should be landing on my bench around this time next month.
The state of my exposure to cryptographic libraries
2016-09-30 14:56 by Ian
This is a quick overview of the cryptographic libraries I have deep experience with.
The Wrongness: Route and Identity
2016-09-25 01:46 by Ian
Of all the species of Wrongness I commonly observe in the wild, the conflation of Route and Identity is of particular concern at layer 7 of the OSI stack.
My collection of C-related rants
2016-09-24 22:54 by Ian
The thing that needs to be made clear is this: C is a permanent fixture. It is not going anywhere in your lifetime. You can use it, or not.
Intro to DTLS
2016-09-24 21:25 by Ian
This post is aimed at technical readers who know what TLS is used for, but may know nothing about its operation. It is also an attempt to explain why DTLS was developed, and how it applies to IoT.
Symmetrical asymmetries
2016-09-24 21:10 by Ian
This is one of a series of posts I will be writing that cover various security-related algorithms. This post will be a brief survey of the two major classes of reversible encryption algorithms.
CPLD is ready-to-rock
2016-07-04 00:03 by Ian
As of today, the CPLD is a solved-problem. All the design goals detailed in my prior post are satisfied and have been tested up-to ~5MHz input clock.