CPLD is ready-to-rock
2016-07-04 00:03 by Ian
As of today, the CPLD is a solved-problem. All the design goals detailed in my prior post are satisfied and have been tested up-to ~5MHz input clock.
IDE Interface in a Xilinx 9572 CPLD
2009-05-16 01:39 by Ian
This is my first attempt at making an actual ASIC.