Digitabulum r2 PCBs have arrived
2017-02-18 01:11 by Ian
The r2 hardware arrived Friday. Had CPLD images flashed by Saturday. I'm crazy-busy writing enough firmware for the ESP32 to test it. Until then, photos...
CPLD is ready-to-rock
2016-07-04 00:03 by Ian
As of today, the CPLD is a solved-problem. All the design goals detailed in my prior post are satisfied and have been tested up-to ~5MHz input clock.
Digitabulum Design Choices: CPLD
2016-03-12 23:15 by Ian
This is the third post in a series of posts detailing the rationale for design choices in our motion capture glove. I will try and anticipate questions that informed users will ask. This post will discuss the sequence of choices that culminated in r0's CPLD and give some indications of what was changed.
IDE Interface in a Xilinx 9572 CPLD
2004-02-21 01:39 by Ian
This is my first attempt at making an actual ASIC.